BENCH=bench
MODEL=ultraMips
PLIC=/usr/local/bin/iverilog-vpi
VC=/usr/local/bin/iverilog

.PHONY: help


help:
	@echo "The following make targets are supported:" ;\
	echo " dut    - builds the DUT";\
	echo " cmodel - builds the C model";\
	echo " bench  - builds the testbench";\
	echo " run    - runs the testbench";\
	echo " expand - expands veritedium directives (autoargs, inst etc.)";\
	echo " indent - automatically indents verilog and c files" ;\
	echo " clean  - cleans testbench and intermediate files" ;\
	echo " help   - show this information";\

bench: expand dut cmodel 

indent:
	emacs --batch -l ./verilog-mode.el *.v -f verilog-batch-indent
	indent -linux *.c *.h
	rm *~

expand:
	emacs --batch -l ./verilog-mode.el bench.v -f verilog-batch-delete-auto -f save-buffer
	emacs --batch -l ./verilog-mode.el bench.v -f verilog-auto -f save-buffer
	rm *~

cmodel:
	$(PLIC) *.c --name=$(MODEL)

dut: 
	$(VC) -o $(MODEL).vvp $(BENCH).v ../rtl/*.v

run:
	vvp -m$(MODEL) -M. $(MODEL).vvp 

clean:
	rm -rf *.o *~ *.vpi *.vvp *.vcd *.txt

